標題: A parallel coupled-line filter using VLSI backend interconnect with high resistivity substrate
作者: Chen, C. C.
Kao, H. L.
Chiang, K. C.
Chin, Albert
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: parallel coupled-line filter;VLSI;high resistivity substrate;millimeter-wave
公開日期: 1-Jan-2006
摘要: This paper reports our progress in developing parallel coupled-line filters based on Si-based VLSI backend interconnects for millimeter-wave applications. The resonant frequency of this coupled-line filter increases with increasing spacing-gap and with increasing IDM thickness. By using high resistivity substrate, the parallel coupled-line band-pass filter is extremely effective in reducing substrate loss, and also provides very low insertion loss, even at the millimeter-wave regime. In addition, the parallel coupled-line filter suitable for advanced system-on-a-chips at the millimeter wave application achieves high performance characteristics, which show low insertion loss, wide band, and compatibility with standard VLSI process.
URI: http://dx.doi.org/10.1007/s10762-006-9051-5
http://hdl.handle.net/11536/12928
ISSN: 0195-9271
DOI: 10.1007/s10762-006-9051-5
期刊: INTERNATIONAL JOURNAL OF INFRARED AND MILLIMETER WAVES
Volume: 27
Issue: 1
起始頁: 93
結束頁: 105
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