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dc.contributor.author陳巍仁 zh_TW
dc.date.accessioned2016-12-20T03:56:43Z-
dc.date.available2016-12-20T03:56:43Z-
dc.date.issued2016en_US
dc.identifier.govdocMOST105-2221-E009-170 zh_TW
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=11877022&docId=484714en_US
dc.identifier.urihttp://hdl.handle.net/11536/131792-
dc.description.abstract zh_TW
dc.description.abstract en_US
dc.description.sponsorship科技部 zh_TW
dc.language.isozh_TWen_US
dc.subject zh_TW
dc.subject en_US
dc.title混合信號積體電路之核心設計技術-子計畫二:100 Gbps/400 Gbps 多通道, 高性能串列傳輸接收機zh_TW
dc.title100 Gbps/400 Gbps Multi-Channel, High Performance Serial Link Receiveren_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系及電子研究所 zh_TW
Appears in Collections:Research Plans