完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Sung, HC | en_US |
dc.contributor.author | Lei, TF | en_US |
dc.contributor.author | Huang, CM | en_US |
dc.contributor.author | Kao, YC | en_US |
dc.contributor.author | Lin, YT | en_US |
dc.contributor.author | Wang, CS | en_US |
dc.date.accessioned | 2014-12-08T15:18:15Z | - |
dc.date.available | 2014-12-08T15:18:15Z | - |
dc.date.issued | 2005-10-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.44.7377 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13193 | - |
dc.description.abstract | A new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described in this paper. This novel structure can significantly enhance coupling capacitance between the Source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6AV, which is characterized by a newly developed methodology for program vs disturb window characterization. For cell size scaling, comparable sort-1 and sort-2 yields are demonstrated using the new cell with a shorter floating length and a shallower source junction. To understand the relationship between source coupling ratio (SCR) and the program/erase mechanism, an insightful discussion on the program and erase mechanisms for our split-gate flash cell is also shown in this paper. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | flash | en_US |
dc.subject | EEPROM | en_US |
dc.subject | split-gate | en_US |
dc.subject | source-side injection | en_US |
dc.subject | source coupling | en_US |
dc.title | New triple self-aligned (SA3) split-gate flash cell with T-shaped source coupling | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/JJAP.44.7377 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | en_US |
dc.citation.volume | 44 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 7377 | en_US |
dc.citation.epage | 7383 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000232739300034 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |