High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Abstract

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width similar to 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG polySi JL FETs show excellent electrical performance in terms of low gate overdrive voltage (V-G-V-TH = 2 V), extremely nearideal subthreshold swing (S.S.) similar to 68 mV/decade, steep average subthreshold swing (A.S.S.) similar to 73 mV/decade, smaller drain-induced barrier lowering similar to 9 mV/V, a higher ON/OFF current ratio similar to 1.1 x 10(8) (VD = 1 V), and a better field-effect mobility (mu(FE)) similar to 35 (cm(2)/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications.