標題: | A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications |
作者: | Khwa, Win-San Chang, Meng-Fan Wu, Jau-Yi Lee, Ming-Hsiu Su, Tzu-Hsiang Yang, Keng-Hao Chen, Tien-Fu Wang, Tien-Yen Li, Hsiang-Pang Brightsky, Matthew Kim, Sangbum Lung, Hsiang-Lan Lam, Chung 交大名義發表 National Chiao Tung University |
關鍵字: | MLC;multilevel cell;PCM;PCRAM;resistance drift;write driver |
公開日期: | 一月-2017 |
摘要: | For multilevel cell (MLC) phase change memory (PCM), resistance drift ( R-drift) phenomenon causes cell resistance to increase with time, even at room temperature. As a result, the fixed-threshold-retention (FTR) raw-bit-error-rate (RBER) surpasses practical ECC correction ability within hours after being programmed. This study proposes a resistance drift compensation (RDC) scheme to mitigate R-drift issue. The proposed RDC scheme realizes PCM drift compensation and features RDC pulse to suppress ECC decoding failure. The proposed approach was validated using a 90-nm 128M cells PCM chip and an FPGA-based memory controller verification system. The MLC PCM FTR RBER has been suppressed by over 100x, thereby bringing it within ECC capability. The effectiveness of the RDC scheme was verified up to 106 cycles. |
URI: | http://dx.doi.org/10.1109/JSSC.2016.2597822 http://hdl.handle.net/11536/133302 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2016.2597822 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 52 |
Issue: | 1 |
起始頁: | 218 |
結束頁: | 228 |
顯示於類別: | 期刊論文 |