完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Chih-Sheng | en_US |
dc.contributor.author | Liu, Wei-Lun | en_US |
dc.contributor.author | Yeh, Wei-Ting | en_US |
dc.contributor.author | Chang, Li-Wen | en_US |
dc.contributor.author | Hwu, Wen-Mei W. | en_US |
dc.contributor.author | Chen, Sao-Jie | en_US |
dc.contributor.author | Hsiung, Pao-Ann | en_US |
dc.date.accessioned | 2017-04-21T06:50:02Z | - |
dc.date.available | 2017-04-21T06:50:02Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.isbn | 978-1-4244-6252-0 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134391 | - |
dc.description.abstract | In this paper, we propose a parallel design of Viterbi decoder for Software-Defined Radio (SDR). Our method implements a divide-and-conquer approach by tiling decoding sequences, performing independent speculated Viterbi decoding, and merging partial candidate paths into the final path. For each independent Viterbi decoding, the best path is selected by calculating Hamming distances trellis-by-trellis in parallel. Our method shows up to 14.6x speedup on an NVIDIA 8800 GTX over a sequential C implementation on a 2.4GHz Intel Core 2 CPU. Also, compared with existing GPU-based implementation in [3], our method outperforms up to 2.5x. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Software-Defined Radio (SDR) | en_US |
dc.subject | Viterbi Decoder | en_US |
dc.subject | Graphics Processing Units (GPUs) | en_US |
dc.subject | Compute Unified Device Architecture (CUDA) | en_US |
dc.title | A Tiling-Scheme Viterbi Decoder in Software Defined Radio for GPUs | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2011 7TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING (WICOM) | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000305092100042 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |