Process Technological Analysis for Dynamic Characteristic Improvement of 16-nm HKMG Bulk FinFET CMOS Circuits

Abstract

In this work, we study dynamic characteristic of digital CMOS circuits of 16-nm HKMG bulk FinFET devices by optimizing fabrication windows of inline parameters. Key process parameters are ranked according to integrated circuit quiescent current (IDDQ) and delay of ring oscillators. IDDQ and delay are affected by the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant. Dependencies of operational frequency and IDDQ on the on-state current ratio of N/P FinFET devices are examined. By replacing dual spacers with single ones will improve the uniformity of implantation; consequently, the variation of IDDQ can be reduced from 252 to 37 nA significantly.