A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC

Abstract

We present a pulse latch with a measured Vccmin at the circuit of 0.42 V and pulse width of approximately 3 FO4-inverter delays. A wider operating window and reduced dependence on the input rise-time and PVT variations were obtained using a new pulse generator. A pulse in the new generator starts when its input crosses the switching level of its input gate, unlike in the classic text-book-style pulse-generator. An 8 to 10% improvement in power, performance, and area (PPA) of a typical digital SOC is observed when a group of pulse latches is driven by a distributed clock regenerator (OCR). The OCR has the new pulse generator at its input stage and provides pulse clocks to the pulse latches. Experimental results in a 28-nm HKMG process closely match SPICE simulations.