標題: An Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD Applications
作者: Tsai, Hung-Yuan
Yang, Chi-Heng
Chang, Hsie-Chia
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2012
摘要: This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384;124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.
URI: http://hdl.handle.net/11536/134766
ISBN: 978-1-4673-2771-8
期刊: 2012 IEEE Asian Solid State Circuits Conference (A-SSCC)
起始頁: 61
結束頁: 64
Appears in Collections:Conferences Paper