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dc.contributor.authorLin, Chen-Yangen_US
dc.contributor.authorWong, Cheng-Chien_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2017-04-21T06:48:17Z-
dc.date.available2017-04-21T06:48:17Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-2771-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/134767-
dc.description.abstractThis paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k = 1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm(2) core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.en_US
dc.language.isoen_USen_US
dc.titleA 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellisen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE Asian Solid State Circuits Conference (A-SSCC)en_US
dc.citation.spage197en_US
dc.citation.epage200en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000392841900050en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper