標題: | Automatic Loading Detection (ALD) Technique for 92% High Efficiency Interleaving Power Factor Correction (PFC) Over a Wide Output Power of 180W |
作者: | Tsai, Jen-Chive Chen, Chun-Yen Chen, Yi-Ting Ni, Chia-Lung Su, Yi-Ping Chen, Ke-Horng Chen, Yu-Wen Liang, Chao-Chiun Ho, Chang-An Yu, Tun-Hao 電控工程研究所 Institute of Electrical and Control Engineering |
關鍵字: | interleaving power factor correction (PFC);automatic loading detection (ALD) technique;switching power loss |
公開日期: | 2012 |
摘要: | the proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W. |
URI: | http://hdl.handle.net/11536/134771 |
ISBN: | 978-1-4673-2771-8 |
期刊: | 2012 IEEE Asian Solid State Circuits Conference (A-SSCC) |
起始頁: | 229 |
結束頁: | 232 |
顯示於類別: | 會議論文 |