標題: A Hardware-Efficient Deblocking Filter Design for HEVC
作者: Fang, Chih-Chung
Chen, I-Wen
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Deblocking filter;HEVC;VLSI architecture design
公開日期: 2015
摘要: This paper presents a hardware-efficient deblocking filter architecture for High Efficiency Video Coding (HEVC) to reduce visual artifacts at block boundaries. This design proposes an interleaved scheduling to reduce the intermediate data storage to be 1536 bits instead of whole 8192 bits. The implementation with 90 nm CMOS technology can support real-time deblocking operation of 7682x4320@30 fps under 141.5 MHz with only 31K gate count.
URI: http://hdl.handle.net/11536/134779
ISBN: 978-1-4799-8391-9
ISSN: 0271-4302
期刊: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
起始頁: 1786
結束頁: 1789
Appears in Collections:Conferences Paper