完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Yu-Chun | en_US |
dc.contributor.author | Shiue, Muh-Tian | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.date.accessioned | 2017-04-21T06:49:33Z | - |
dc.date.available | 2017-04-21T06:49:33Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-3827-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/134991 | - |
dc.description.abstract | Decision feedback equalizer (DFE) uses a feedback path to cancel post-cursor IS!, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10Gbps multiplexer-based lookahead DFE. | en_US |
dc.language.iso | en_US | en_US |
dc.title | 10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | en_US |
dc.citation.spage | 1839 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000275929801140 | en_US |
dc.citation.woscount | 2 | en_US |
顯示於類別: | 會議論文 |