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dc.contributor.authorLin, Yu-Chunen_US
dc.contributor.authorShiue, Muh-Tianen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2017-04-21T06:49:33Z-
dc.date.available2017-04-21T06:49:33Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-3827-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/134991-
dc.description.abstractDecision feedback equalizer (DFE) uses a feedback path to cancel post-cursor IS!, and this feedback path will also cause the limitation of its maximum throughput rate. This paper proposes a new lookahead method to break the feedback path for multi-gigabit DFE design. After lookahead computation, each paralleled sub-circuit has the same throughput rate as original one. Therefore, the total throughput rate is proportional to the parallelization factor. The computation complexity of the proposed architecture is lower than that of multiplexer-based lookahead DFE if the tap number of the feedback filter is large. It is shown that the new method saves 10% hardware complexity for an 8 taps feedback filter DFE and 98% hardware complexity for a 12 taps feedback filter DFE in comparison to a 10Gbps multiplexer-based lookahead DFE.en_US
dc.language.isoen_USen_US
dc.title10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loopen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5en_US
dc.citation.spage1839en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000275929801140en_US
dc.citation.woscount2en_US
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