完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lu, HungWen | en_US |
dc.contributor.author | Su, ChauChin | en_US |
dc.contributor.author | Liu, Chien-Nan | en_US |
dc.date.accessioned | 2017-04-21T06:49:12Z | - |
dc.date.available | 2017-04-21T06:49:12Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-1-4244-2018-6 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/CICC.2008.4672068 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135105 | - |
dc.description.abstract | A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Buffer | en_US |
dc.subject | I/O | en_US |
dc.subject | SSN | en_US |
dc.title | A Scalable Digitalized Buffer for Gigabit I/O | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1109/CICC.2008.4672068 | en_US |
dc.identifier.journal | PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE | en_US |
dc.citation.spage | 241 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000262643900055 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |