完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLu, HungWenen_US
dc.contributor.authorSu, ChauChinen_US
dc.contributor.authorLiu, Chien-Nanen_US
dc.date.accessioned2017-04-21T06:49:12Z-
dc.date.available2017-04-21T06:49:12Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2018-6en_US
dc.identifier.urihttp://dx.doi.org/10.1109/CICC.2008.4672068en_US
dc.identifier.urihttp://hdl.handle.net/11536/135105-
dc.description.abstractA serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.en_US
dc.language.isoen_USen_US
dc.subjectBufferen_US
dc.subjectI/Oen_US
dc.subjectSSNen_US
dc.titleA Scalable Digitalized Buffer for Gigabit I/Oen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/CICC.2008.4672068en_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage241en_US
dc.citation.epage+en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000262643900055en_US
dc.citation.woscount0en_US
顯示於類別:會議論文