標題: | Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack |
作者: | Liu, Chien Chen, Ping-Guang Xie, Meng-Jie Liu, Shao-Nong Lee, Jun-Wei Huang, Shao-Jia Liu, Sally Chen, Yu-Sheng Lee, Heng-Yuan Liao, Ming-Han Chen, Pang-Shiu Lee, Min-Hung 電子物理學系 Department of Electrophysics |
公開日期: | 四月-2016 |
摘要: | The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2V switching voltage) to realize next-generation state-of-the-art devices. (C) 2016 The Japan Society of Applied Physics |
URI: | http://dx.doi.org/10.7567/JJAP.55.04EB08 http://hdl.handle.net/11536/135179 |
ISSN: | 0021-4922 |
DOI: | 10.7567/JJAP.55.04EB08 |
期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS |
Volume: | 55 |
Issue: | 4 |
顯示於類別: | 會議論文 |