標題: | Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications |
作者: | Wu, Tse-Ching Chen, Chien-Ju Chen, Yin-Nien Hu, Vita Pi-Ho Su, Pin Chuang, Ching-Te 電子物理學系 Department of Electrophysics |
關鍵字: | Verilog-A model;hybrid circuit;tunneling FET;FinFET;latch;work function variation;fin line-edge roughness |
公開日期: | 2015 |
摘要: | In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage (CMOS)-M-2 latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (< 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V. |
URI: | http://hdl.handle.net/11536/135744 |
ISBN: | 978-1-4673-9094-1 |
期刊: | 2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) |
起始頁: | 339 |
結束頁: | 344 |
Appears in Collections: | Conferences Paper |