ESD Protection Design with Latchup-Free Immunity in 120V SOI Process

Abstract

Electrostatic discharge (ESD) protection with lowvoltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-mu m 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.