標題: Logic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Process
作者: Yang, Chih-Chao
Hsieh, Tung-Ying
Huang, Wen-Hsien
Wu, Tsung-Ta
Wang, Hsing-Hsiang
Shen, Chang-Hong
Kao, Ming-Hsuan
Yeh, Wen-Kuan
Chang, Meng-Fan
Wu, Meng-Chyi
Shieh, Jia-Min
光電工程學系
Department of Photonics
關鍵字: 3DIC;monolithic 3D;low thermal budget;laser anneal
公開日期: 2015
摘要: High performance 3D sequentially stackable nanowire FETs and non-volatile memories (NVMs) with threshold voltage engineering and driving current boosting technologies were demonstrated by using low thermal budget nanosecond laser crystallization and laser activation technologies. The local heating laser process without damaging the underlying device/circuit realizes the across -layer and in -layer integration of high-speed 3ps logic circuits and 1-T 100ns plasma-MONOS NVMs as well as low driving-voltage 6T SRAMs with static noise margin (SNM) of 280 mV. Such logic/memory hybrid 3D sequentially integrated circuit provides power efficient computing and storage. Moreover, the monolithically stacking of Si thin-film energy harvester envisions lower power and low cost 3D(+)IC for internet of things.
URI: http://hdl.handle.net/11536/135851
ISBN: 978-1-5090-0259-7
期刊: 2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S)
顯示於類別:會議論文