標題: Subthreshold SRAM Macro Design with Pulse-Controlled Dynamic Voltage Scaling (PC-DVS)
作者: Zhao, Jun-Kai
Chiu, Yi-Wei
Jou, Shyh-Jye
Chu, Yuan-Hua
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2014
摘要: In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.
URI: http://hdl.handle.net/11536/135887
ISBN: 978-1-4799-5127-7
ISSN: 2163-9612
期刊: 2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)
起始頁: 114
結束頁: 115
Appears in Collections:Conferences Paper