標題: Design of a power-reduction viterbi decoder for WLAN applications
作者: Lin, CC
Shih, YH
Chang, HC
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: add-compare-select;path merging;path prediction;survivor memory;Viterbi decoder
公開日期: 1-Jun-2005
摘要: In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-mu m standard CMOS process. The test results show that 30 similar to 40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.
URI: http://dx.doi.org/10.1109/TCSI.2005.849106
http://hdl.handle.net/11536/13606
ISSN: 1057-7122
DOI: 10.1109/TCSI.2005.849106
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 52
Issue: 6
起始頁: 1148
結束頁: 1156
Appears in Collections:Articles


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