完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tsai, Hui-Wen | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.date.accessioned | 2017-04-21T06:49:51Z | - |
dc.date.available | 2017-04-21T06:49:51Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-9928-6 | en_US |
dc.identifier.issn | 1946-1550 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136115 | - |
dc.description.abstract | A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS devices through special circuit design can effectively reduce the latchup trigger current that injecting into the core circuit blocks. Therefore, the latchup immunity of I-test with positive or negative trigger current applied at the I/O pins can be significantly improved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Improve Latch-up Immunity by Circuit Solution | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015) | en_US |
dc.citation.spage | 527 | en_US |
dc.citation.epage | 530 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380466200135 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |