Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering

Abstract

According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V-BD) and low holding voltage (V-h) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency (V-t1=8.1V) without suffering from low V-BD and latch-up issues.