標題: | Low-Trigger ESD Protection Design with Latch-Up Immunity for 5-V CMOS Application by Drain Engineering |
作者: | Chiang, Chun Chang, Ping-Chen Chao, Mei-Ling Tang, Tien-Hao Su, Kuan-Cheng Ker, Ming-Dou 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-Jan-2017 |
摘要: | According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (V-BD) and low holding voltage (V-h) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency (V-t1=8.1V) without suffering from low V-BD and latch-up issues. |
URI: | http://hdl.handle.net/11536/147120 |
ISSN: | 1946-1550 |
期刊: | 2017 IEEE 24TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA) |
Appears in Collections: | Conferences Paper |