標題: | A Variable-Voltage Low-Power Technique for Digital Circuit System |
作者: | Xiao, An-Tai Miao, Yung-Siang Cheng, Ching-Hwa Guo, Jiun-In 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2016 |
摘要: | A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising and falling signals fanin FDCA to generate an adjustable high-low signal to control VFA generates high-low cycling swing voltage. When the clock is at positive-level, a generic positive-edge digital circuit will need large operation current. CK-Vdd supply high-voltage to the digital circuit at this time. On the other hand, when the clock signal transfers to the low-level, CK-Vdd can supply low-voltage to reduce power consumption. From reducing the supply current to the digital circuit at low-level clock, the digital circuit power consumption can be reduced. We implement the CK-Vdd technique in a H. 264 video decoder test chip based on TSMC 90 nm CMOS process. The result shows that when CK-Vdd voltage is 0.7v similar to 0.9v it can save average 32% power consumption. To the maximum, decoder chip can save as high as 45% power consumption. |
URI: | http://hdl.handle.net/11536/136175 |
ISBN: | 978-1-4673-9569-4 |
ISSN: | 2153-6961 |
期刊: | 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) |
起始頁: | 13 |
結束頁: | 14 |
顯示於類別: | 會議論文 |