Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity

Abstract

Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-mu m BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.