標題: Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
作者: Tang, Kai-Neng
Liao, Seian-Feng
Ker, Ming-Dou
Chiou, Hwa-Chyi
Huang, Yeh-Jen
Tsai, Chun-Chien
Jou, Yeh-Ning
Lin, Geeng-Lih
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2015
摘要: Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-mu m BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.
URI: http://hdl.handle.net/11536/136217
ISBN: 978-1-4799-6670-7
ISSN: 2162-7673
期刊: 2015 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)
起始頁: 325
結束頁: 328
顯示於類別:會議論文