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dc.contributor.authorHuang, Shen-Juien_US
dc.contributor.authorChen, Sau-Geeen_US
dc.date.accessioned2017-04-21T06:48:56Z-
dc.date.available2017-04-21T06:48:56Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-4833-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/136331-
dc.description.abstractThis paper presents new rotator architecture for FFT computation. The proposed architecture consists of cascaded multiplier-less cells, and each cell stage performs partial twiddle factor multiplications with low-complexity adders and multiplexers. Besides, for further area reduction, each cell is optimized with the technique of common subexpression sharing. Since those twiddle factors involved in computation are realized with multipliers generated on-the-fly by a scheme of coefficient selection, the proposed architecture doesn\'t require memory space to store any twiddle factors. Variable FFT lengths ranging from 64 similar to 32768 points can be supported by flexibly adding or removing some cell stages, depends on FFT length. Compared to CORDIC-based architectures, the proposed architecture has lower latency. The implementation results show that the proposed architecture is area-efficient and is suitable for either pipelined or memory based FFT architectures.en_US
dc.language.isoen_USen_US
dc.subjectFast Fourier Transform (FFT)en_US
dc.subjectRotatoren_US
dc.subjecttwiddle factoren_US
dc.subjectCORDICen_US
dc.titleA New Memoryless and Low-latency FFT Rotator Architectureen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC)en_US
dc.citation.spage180en_US
dc.citation.epage183en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000380456800023en_US
dc.citation.woscount1en_US
Appears in Collections:Conferences Paper