標題: | Cost-Efficiency FFT Using Hardware-Reduction and Dynamic Current Scaling Approaches |
作者: | Chen, Ying-Liang Hsu, Terng-Yin 資訊工程學系 Department of Computer Science |
關鍵字: | Fast Fourier Transform (FFT);Pipelined-based Architecture;Dynamic Current Scaling (DCS) |
公開日期: | 2014 |
摘要: | In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy. |
URI: | http://hdl.handle.net/11536/136332 |
ISBN: | 978-1-4799-4833-8 |
期刊: | 2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC) |
起始頁: | 184 |
結束頁: | 187 |
顯示於類別: | 會議論文 |