標題: Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration
作者: Hu, Yu-Chen
Chang, Yao-Jen
Wu, Chun-Shen
Cheng, Yung Mao
Chen, Wei Jen
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2014
摘要: In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270 degrees C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn mu-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 mu m bump pitch, 40 mu m diameter of Cu/Sn mu-bump and 50 mu m diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.
URI: http://hdl.handle.net/11536/136338
ISBN: 978-1-4799-7727-7
期刊: 2014 9TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT)
起始頁: 290
結束頁: 293
Appears in Collections:Conferences Paper