標題: ERROR-RESILIENT SEQUENTIAL CELLS WITH SUCCESSIVE TIME BORROWING FOR STOCHASTIC COMPUTING
作者: Liu, Wei-Chang
Chan, Ching-Da
Huang, Shuo-An
Lo, Chi-Wei
Yang, Chia-Hsiang
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Error-resilient circuit;sequential cell;time borrowing;stochastic computing
公開日期: 2016
摘要: This paper presents error-resilient sequential building blocks with time-borrowing capability without extra latches and generated clocks. The circuits are able to recover the timing errors caused by PVT variations and/or over-voltage scaling by up to half a cycle. Unlike prior works, the timing errors can be recovered dynamically through successive time borrowing without stalled cycles, retaining a constant throughput. The circuit structure can be applied to both ASICs and microprocessors. The proposed sequential cells are highly compatible with current cell-based IC design flow, for both feed-forward and feedback datapaths. As a proof of concept, a design with key DSP building blocks has been verified. The results show that the performance of the DSP modules is improved by 13-15% in the worst-case operation condition, yielding a promising solution for stochastic computing under an unreliable operation condition.
URI: http://hdl.handle.net/11536/136368
ISBN: 978-1-4799-9988-0
ISSN: 1520-6149
期刊: 2016 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING PROCEEDINGS
起始頁: 6545
結束頁: 6549
Appears in Collections:Conferences Paper