標題: 28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
作者: Hsu, Wei-Shen
Huang, Po-Tsang
Wu, Shang-Lin
Chuang, Ching-Te
Hwang, Wei
Tu, Ming-Hsien
Yin, Ming-Yu
電子工程學系及電子研究所
電機工程學系
Department of Electronics Engineering and Institute of Electronics
Department of Electrical and Computer Engineering
公開日期: 2016
摘要: In this paper, an ultra-low-power near-/sub-threshold first-in-firstout (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512x16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.
URI: http://hdl.handle.net/11536/136381
ISBN: 978-1-4673-9498-7
期刊: 2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
Appears in Collections:Conferences Paper