標題: Electrical Testing Structure for Stacking Error Measurement in 3D Integration
作者: Lee, Shih-Wei
Kuo, Shu-Chiao
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2016
摘要: A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.
URI: http://hdl.handle.net/11536/136431
ISBN: 978-1-4673-9478-9
ISSN: 1930-8868
期刊: 2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)
Appears in Collections:Conferences Paper