Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tseng, Sheng-Che | en_US |
dc.contributor.author | Wei, Hung-Ju | en_US |
dc.contributor.author | Syu, Jin-Siang | en_US |
dc.contributor.author | Meng, Chinchun | en_US |
dc.contributor.author | Tsung, Kuan-Chang | en_US |
dc.contributor.author | Huang, Guo-Wei | en_US |
dc.date.accessioned | 2014-12-08T15:19:13Z | - |
dc.date.available | 2014-12-08T15:19:13Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-2801-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13767 | - |
dc.description.abstract | This paper proposes a true 50% duty-cycle highspeed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 mu m SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 50% duty cycle | en_US |
dc.subject | divide-by-N | en_US |
dc.subject | prescaler | en_US |
dc.subject | SiGe HBT | en_US |
dc.title | True 50% Duty-Cycle High-Speed Divider with the Modulus of Odd Numbers | en_US |
dc.type | Article | en_US |
dc.identifier.journal | APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 | en_US |
dc.citation.spage | 305 | en_US |
dc.citation.epage | 308 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000279924300078 | - |
Appears in Collections: | Conferences Paper |