應用於音頻之低電壓 SAR-DSM 類比數位轉換器

Abstract

三角積分調變器於音頻訊號處理中使用非常廣泛，其特性於頻譜上具有雜訊整形能力，原理是利用迴路濾波器與超取樣，來提高整體解析度，但是非常仰賴積分器之轉移函數，進而使得放大器設計規格提高，另一個問題則是三角積分調變器的動態範圍，通常輸入訊號大過 0.5 倍的全擺幅時，訊噪比會急遽下滑。 連續漸進式類比數位轉換器，通常擁有約 10 bits 解析度，以及接近 100 MHz 的速度，因為不需要利用到放大器，功耗大幅下降，是現行低功耗應用很流行的電路，並且電路複雜度較低，實現起來往往容易許多，但對於比較器設計需要嚴謹的驗證，規格往往會被比較器與電容匹配程度所限制。 本篇論文描述一個 1V，低電壓 CMOS 混合式類比數位轉換器，架構上使用兩種不同型式之轉換器，其中包含一個低精準度的連續漸進式類比數位轉換器，以及一個低階三角積分調變器，此系統主要應用於音頻訊號處理。 此混合式類比數位轉換器，使用兩者各自的優點，先使用連續漸進式轉換器，做出粗略的數位值，再將數位值饋入三角積分調變器，處理殘值，最後得到高解析度的結果，由於調變器處理的是殘值，動態範圍會提升。 我們架構上選定 6 bits 之連續漸進式類比數位轉換器與二階 1 bit 之三角積分調變器，透過兩組電容陣列，來處理輸入訊號，並使用數據權重平均技術降低饋入三角積分調變器的電壓誤差，目標是達到 90dB 訊躁比，整體設計流程經過 MATLAB 與 Verilog-A 行為驗證，電路模擬過程使用 TSMC 90nm COMS 製程技術。

DSM ADCs is widely used in audio signal processing. It can perform noise shaping on spectrum, and the priciple is from loop filter (LF) and over-sampling to achieve high resolution. The transfer function of the integrators in LF dominates performance, that is a issue about designing high specification operational-amplifier (OP). Another issue is the dynamic range (DR) of DSM ADC, which decreases rapidly when input signal is larger than half sacle. SAR ADCs can achieve about 10~Bit resolution and 100~MHz sampling rate. Its power dissipation is quite low because of discarding the OP circuit. In modern low-power circuit, it is very common to use. And the complexity of circuit design is less than other ADCs if we want to implement. As to circuit design, the comparator dominates performance that it needs rigorously verifying. The specifications usually are limited by comparator and capacitors mismatching. This thesis described the design of a 1~V low voltage CMOS analog-to-digital converters (ADCs), which is to be used in audio application. The ADC combines with two different-type ADC, one is the successive approximation register (SAR) ADC, and the other is delta-sigma modulator (DSM) ADC. The hybrid ADC take advantages from this two ADCs above. The input siganl first is processed by SAR ADC to get coarse digital code. Then applying the code to DSM ADC to process residue, and we get the high resolution result finally. The residue is pretty low that the DR of DSM would increase. The proposed ADC architeture are a 6 bits SAR ADC and a second-order 1 bit DSM ADC. To process signal between this two ADC, we need two arrays of capacitors. The data weighted averaging (DWA) technique is used to reduce voltage error. Our target is to achieve 90~dB signal-to-noise ratio (SNR). The behavior design is verified by MATLAB and Verilog-A. We use TSMC 90nm COMS process in circuit simulation.