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dc.contributor.authorSung, HCen_US
dc.contributor.authorLei, TFen_US
dc.contributor.authorHsu, THen_US
dc.contributor.authorKao, YCen_US
dc.contributor.authorLin, YTen_US
dc.contributor.authorWang, CSen_US
dc.date.accessioned2014-12-08T15:19:37Z-
dc.date.available2014-12-08T15:19:37Z-
dc.date.issued2005-03-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2004.842643en_US
dc.identifier.urihttp://hdl.handle.net/11536/13958-
dc.description.abstractIn this letter, a new methodology for program versus disturb window characterization on split gate Flash cell is presented for the first time. The window can be graphically illustrated in V-wI (word-line)-V-ss (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program, bias variations. This methodology was successfully implemented in 0.18-mum triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.en_US
dc.language.isoen_USen_US
dc.subjectdisturben_US
dc.subjectFlash memoryen_US
dc.subjectoperation windowen_US
dc.subjectprogramen_US
dc.subjectsplit-gateen_US
dc.titleNovel program versus disturb window characterization for split-gate flash cellen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2004.842643en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume26en_US
dc.citation.issue3en_US
dc.citation.spage194en_US
dc.citation.epage196en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000227262500023-
dc.citation.woscount4-
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