Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Applications

Abstract

在應用於高密度神經感測生理訊號之訊號擷取系統中，感測放大器、類比數位轉換器以及數位訊號處理器所佔的面積以及功耗是嚴峻的挑戰。本論文提出了一個具自我校正功能11位元功耗面積最佳化之類比數位轉換器。在本設計中，11位元類比數位轉換器分成粗調類比數位轉換器負責前三個MSB，細調類比數位轉換器負責剩下的八個位元以達到降低電容大小的目的，雙供應電壓分別供給數位電路以及類比電路以降低整體功耗，並加入位準調整器當作數位與類比電路間的溝通平台。藉由電源管理設計以及高臨界電壓元件來解決漏電流問題。為了解決製程變異及寄生電容所造成的誤差碼，提出了自我校正演算法，在一開機時自我偵測誤差並收集數據儲存於暫存器，提供轉換模式時達到即時補償，並以實體電路實現在晶片中提高精準度。整體類比數位轉換器使用台積電90奈米製程，在取樣頻率32千取樣/每秒下的功耗為982 奈瓦。有效位元是9.71位元而品質係數為36.75飛焦/轉換。整體類比數位轉換器之有效面積為0.026平方毫米。

Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented an area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. The proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined based ADC and successive approximation register (SAR) ADC. The three most significant bits are detected by a modified vernier structure delay-line-based ADC. Self-timed power management including dual voltage supply, power-gating and multi-threshold CMOS device are employed. To improve accuracy of ADC, the capacitance mismatch due to process variation and parasitic capacitance are compensated by self-calibration scheme. The proposed 11 bit ADC is implemented in TSMC 90nm general propose (GP) CMOS technology. Post-sim results indicate that ENOB of 9.71-bits at 32KS/s sampling rate can be achieved with only 982nW power consumption and 0.026-mm2. The FOM of the proposed hybrid ADC is 36.75fJ/conversion-step.