異質晶片之電源供應網路模型化並應用於三維積體電路之實際電路共同合成實體化之研究

Abstract

三維積體電路在當今的消費性電子產品中已經變得越來越實用了，但是在設計的合成與設計的流程上仍存在著一個主要的問題：如何為異質晶片建模並與邏輯晶片進行電源合成並簽核。本論文將提供一個實際的異質晶片之電源供應網路模型供三維積體電路設計使用，我們將藉由設計早期所能得到的資訊，如微凸塊的位置及其所消耗的功率等等，來產出電源供應網路模型。同時，我們會使用此電源供應網路模型來與數位積體電路設計流程的晶片做堆疊，並共同合成電源供應網路，並且確保所有電源網域沒有違反設計規範及電子遷移的錯誤產生。首先，我們會先分析所有異質晶片上供電微凸塊之位置及消耗功率，並根據分析結果來初步生成異質晶片模型之電源供應網路及其電源消耗點。接著將生成的網路用節點分析的方式來計算節點電壓、並使用序列線性規劃法調整電源線的寬度來最佳化我們所提供的異質晶片模型。本異質晶片模型的產出包括DEF檔及商用軟體EDI及EPS所需之檔案，使我們的模型可以供商用軟體來使用並驗證我們的結果。最後，我們會將產出的模型與實際工業用設計的晶片來與我們的模型做堆疊並共同合成出相對應電源網域的所有電源網路。本論文的所使用的數據是由業界IC設計公司所提供的真實三維積體電路堆疊設計所產出的。並且由實驗結果可發現，使用我們所提供的等效模型來合成的電源供應網路可節省約34%的金屬層使用量。

Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous die’s power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous die’s model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.