垂直式砷化銦/銻化鎵異質接面穿隧場效電晶體之最佳化

Abstract

隨著半導體製造技術的演進，直到目前2016年為止半導體科技的技術節點來到10奈米，而未來半導體技術預期將會朝向7/5奈米甚至於三維堆疊發展。然而電晶體密度的增加亦伴隨著晶片功耗密度的升高，因此降低晶片供應電壓及漏電流以降低功耗成為延續摩爾定律的關鍵之一。同時，在元件微縮時還要維持足夠低的次臨界擺幅和高的開關電流比例。近年來如鰭式電晶體、奈米線電晶體等元件的提出將次臨界擺幅推進到相當接近熱場發開關機制的物理極限(60 mV/dec)的程度，其中鰭式電晶體已經被實際應用於業界的先進製程中。最近數種新穎的電晶體概念被提出以突破60 mV/dec次臨界擺幅的限制，如穿隧場效電晶體、負電容場效電晶體及奈米級機電開關等。其中穿隧場效電晶體是利用閘極控制源極與通道間的價帶與導帶間穿隧效應作為開關機制以達到陡峭的開關特性。 然而穿隧場效電晶體的穿隧能障會降低元件的導通電流，因此窄能隙的材料以及異質接面材料被提出應用於穿隧場效電晶體的通道材料以提升導通電流。其中InAs/GaSb異質接面由於其第三型接近第二型的異質接面，可以藉由元件結構的調變或是三元化合物的引入如InGaAs/AlGaSb以得到極低的穿隧能障。文獻指出雙閘極InAs/GaSb穿隧場效電晶體的導通電流可以達到752mA/mm。 垂直式穿隧場效電晶體由於閘極電場與穿隧電流方向平行、與穿隧接面垂直，使得閘極控制穿隧接面的效率相當好，搭配InAs/GaSb的異質接面，可以達到相當高的導通電流。本論文首先將會就垂直式InAs/AlSb/GaSb異質接面穿隧場效電晶體的製程、電性以及模擬進行討論。藉由置入薄AlSb層於InAs/GaSb間可以讓InAs/GaSb間固定的能帶差得以調變以增進元件的導通電流以及開關特性。實驗結果顯示垂直式InAs/AlSb/GaSb異質接面穿隧場效電晶體之導通電流於閘極、汲極偏壓0.4 V下可以達到22 µA/µm2，而汲極偏壓0.1 V下之次臨界擺幅為194mV/dec，而導通關閉電流比例為大於10^3，另外亦藉由實驗結果以及模擬說明側蝕刻深度對於元件的影響。除了電晶體操作特性外，本論文亦會對垂直式InAs/AlSb/GaSb異質接面穿隧場效電晶體於順向偏壓操作下的多峰值負微分電阻現象進行探討並建立物理模型驗證之。 接著本論文亦就垂直式InAs/GaSb異質接面穿隧場效電晶體以TCAD Sentaurus模擬軟體的模擬結果以及模型進行元件設計的最佳化。研究發現垂直式穿隧場效電晶體有下列的臨界電壓不均勻問題：(1) 因側蝕刻而暴露出的InAs表面之表面能態會使得費米能階移近甚至高於導帶、(2)L型的結構使得接面上的閘極通道間耦合不均勻。這些因素會使得垂直式穿隧場效電晶體於穿隧接面上同時有著不同的臨界電壓，進而讓元件的開關特性變差。另外就L型結構產生的本質閘極通道間不均勻耦合，本論文介紹的臨界電壓差模型顯示可以藉由：(1)調變異質接面能帶差、(2) 閘極通道間耦合均勻化以得到相當優異的開關特性。另外就InAs的表面能態導致的元件開關特性劣化問題，亦可以利用雙金屬閘極結構來改善。

The semiconductors technology has entered 10 nanometers generation node by 2016. In the near future, the semiconductors technology will reach 7/5 nanometers generation or even move toward the 3 dimensional stacking. However, accompanying the increase of device density, the heat dissipation of the IC chip becomes a major issue. Hence the reduction of the supply voltage and suppressing the leakage current are important for sustaining the Moore’s law in the future. Meanwhile, the scaling of the transistors dimension requires the transistors to maintain the low subthreshold slope and the high ION/IOFF under low supplied voltage. Recently, several MOSFETs architectures had been proposed to push the switching characteristics close to their thermionic emission physical limitation (60 mV/dec), like finFETs and nanowire FETs. At present, finFET technology has already been applied to the advanced IC fabrication in industry. Recently, several novel transistor concepts have been proposed to further suppress the subthreshold swing to lower than 60 mV/dec, like tunneling FETs, negative capacitance FET and nano-mechanical switching. The switching mechanism of the tunneling FET is the gate-controlled band to band tunneling between source and channel. The tunneling FETs can result in very sharp switching characteristics. The tunneling barrier in tunneling FETs can cause a very low on-current level, hence the narrow bandgap materials and hetero-junction materials have been proposed as channel materials to decrease the tunneling barrier and to enhance the on-current level of tunneling FETs. Using InAs/GaSb hetero-junction with type-III near to type-II hetero-junction, a very small tunneling barrier can be achieved by modulation of the device structure. A recent study indicates that the on-current level of InAs/GaSb double gate tunneling FET can reach 752 mA/mm. Gate electrical field of vertical tunneling FETs is parallel to tunneling direction, and vertical to tunneling junction, which leads to a very good tunneling junction control. With InAs/GaSb hetero-junction, the on-current of tunneling FETs can be much improved. This dissertation will focus on the fabrication, electrical characteristics and simulation of the vertical InAs/AlSb/GaSb tunneling FETs. The insertion of AlSb layer can result in adjustable band offset between InAs/GaSb and the on-current and switching characteristics can be further improved. Experimental results show that the device has 22 µA/µm2 on-current density at VDS = 0.4 V and VGS = 0.4 V, 194 mV/decade subthreshold swing (SS) at VDS = 0.1 V with an Ion/Ioff > 10^3. This study also investigates the impact of lateral etching depth to the device performance. In addition to the transistors characteristics, we also develop the physical model to demonstrate the multi-peak negative differential resistance phenomena which were observed in the forward bias region. TCAD Sentaurus simulation is also performed in this study to optimize the vertical InAs/GaSb tunneling FETs design. It is found that some factors can degrade the switching characteristics of the vertical InAs/GaSb tunneling FET due to the tunneling onset voltage non-uniformity: (1) Fermi pinning at the exposed InAs surface makes the Fermi level pin at close to or even higher than conduction band of InAs, (2) Geometry of L-shape leads to the non-uniformity of gate to channel coupling over the junction. For the inherent coupling non-uniformity issue, the developed model suggests that the tunneling onset voltage non-uniformity can be eliminated by (1) band offset modulation and (2) coupling ratio matching. On the other hand, for the Fermi-pinning induced switching characteristics degradation, the use of dual-metal gate structure can suppress the issue.