通道濃度與硼穿透對多晶矽無接面聚集型鰭式電晶體之影響

Abstract

本研究中，在沒有利用先進的黃光微影技術下，我們利用雙重圖案化(double patterning)的方式成功地製作出具有次三十奈米(sub-30 nm)的通道尺寸。並將此技術應用於開發無接面聚集型(junctionless accumulation mode)P通道(P-channel)的π閘極(Pi-gate)多晶矽(poly-Si)鰭式電晶體(FinFETs)。其中，無接面聚集型P-channel的π閘極多晶矽鰭式電晶體也透過實驗性地研究與完整地討論通道摻雜濃度(doping concentration)對於元件特性的影響，同時也利用材料分析發現，低通道濃度的活化程度僅有0.38%，因此元件容易受到介面能態的影響，並使得電特性降低。當元件的通道尺寸等於35.5 nm × 26.5 nm與通道濃度(channel doping concentration)為5 × 1018 cm-3時，能夠展現優越的電特性，包含陡峭的次臨界擺幅(S.S.) ~ 114 mV/dec.、小的汲極引致能障下降(DIBL) ~ 29 mV/V、以及開關電流比(Ion/Ioff ratio) > 1×108 (VD = 1V)。 除了討論通道濃度的影響以外，我們也在無接面聚集型P-channel的元件上發現硼穿透(boron penetration)的問題，透過額外的源極與汲極的活化情形，我們發現次臨界擺幅有明顯的劣化以及臨界電壓(VTH)有明顯的移動。減少額外的源極與汲極的活化熱預算可以減輕硼穿透的問題，而我們的元件能夠展現出最佳的S.S. ~ 92 mV/dec.以及小的DIBL ~ 20 mV/V，但由於源極與汲極的電阻值較高，並使得開啟電流(Ion)降低。在未來可以透過縮小通道尺寸(sub-10 nm)以及快速退火與微波退火系統來得到最佳的熱預算並且提升元件的電特性與可靠度。因此這些元件是有希望的候選者，並能應用於未來的多功能三維積體電路上。

In this thesis, we used the double patterning to successfully fabricate devices, which with sub-30 nm channel dimension without the use of advanced lithography tools, implantation processes, and plasma treatments. The Pi gate (PG) poly-Si junctionless accumulation mode (JAM) FinFETs with different channel concentration (Nch) have been successfully fabricated and demonstrated. Through the material analysis, we found the devices with lower Nch have lower activation rate due to grain boundary, so the interface state easily affected the carriers and degraded the performance. As the channel dimension (Hfin × Wfin) of 35.5 nm × 26.5 nm and Nch of 5 × 1018 cm-3, the PG JAM FinFETs show the excellent electrical performance, such as steep S.S. ~ 114 mV/dec., small DIBL ~ 29 mV/V and Ion/Ioff ratio > 1×108 (VD = 1V)。 In addition to the effects of Nch, the issue of boron penetration was found on the PG JAM FinFETs by different S/D activation condition: It caused the obvious degradation and positive shift for S.S. and VTH, respectively. It can be mitigated by reducing thermal budget of the additional S/D activation. Our PG JAM FinFETs show the best S.S. ~ 92 mV/dec., DIBL ~ 20 mV/V. But this lowers the Ion due to the higher source/drain resistance. Moreover, we successfully separated and systematically quantitated these effects of charges, which resulted from boron penetration. The performance and reliability will be improved by scaling down channel dimension (sub-10 nm), rapid thermal annealing (RTA) and microwave annealing (MWA) in the future. Therefore, these devices are promising candidates for future multi-functional 3-D integrated circuit (IC) applications.