適用於正反器時序電路的時鐘樹老化容忍設計

Abstract

電路性能是最近十年以來，設計電路的時候，最需要考慮的因素之一。 本論文中，利用時間借取/偷竊，去優化時鐘樹/網路，以降低時鐘週期，來改善整個電路的性能。此外，邏輯閘的延遲會因老化而增加，改變了 電路的時序。本論文中，我們提出了一個方法，在給定的晶片壽命之下，去改善時序電路的性能。所提出的方法是，透過將可靠度改進單元︰佔空比轉換器（DCC），加插到時序電路的時鐘樹中，就可以容忍電路老化。 通過改變時鐘樹/網絡中的時鐘緩衝器的負偏壓不穩定性(BTI)，DCC就可以來控制因老化而產生的時鐘偏移（AICS）。通過時間借取/偷竊的技術，可以降低時序電路的時鐘週期，改善電路性能。 我們的目標是，在給定的壽命規格（如10年）和電路的老化模型的情況下，通過利用AICS的時間借取/偷竊，來改善時鐘週期。此外，我們嘗試反覆在時鐘樹內進行「複製緩衝器」，進一步改善電路性能。為了使實驗結果更加精準，除了暫存器之間的邏輯路徑之外，同時也考慮連接到輸入端口，或者輸出端口的路徑。

Circuit performance has been a key design constraint for over a decade. Time borrowing/stealing of clock tree/network optimization was proposed for improving the overall performance in terms of clock period. In addition, aging effects reveal themselves as gate delays increase, which cause circuit timing changed. In this paper, we propose to improve performance of a sequential circuit for specific circuit lifetime. The proposed methodology is to tolerant aging by inserting reliability improvement units – duty cycle con-verters (DCCs) into the clock tree of a sequential circuit. DCCs control the aging-induced clock skew (AICS) by manipulating Bias Temperature Insta-bility (BTI)-induced aging behavior of clock buffers in clock tree/network. By the technique of time borrowing/stealing, circuit performance can be im-proved by lowering the clock period of the sequential circuit. Our objective is to improve clock period by time borrowing/stealing taking advantage of AICS. A lifetime spec (e.g. 10 years) and the aging model of a circuit are given. Furthermore, we try to add the work of clock buffer duplications and considering paths which connect to input port or output port.