基於工作週期轉換器之電路老化容忍設計

Abstract

隨著半導體製程的進步，奈米級晶片之可靠度問題已成為高階積體電路設計的一大挑戰；其中，電路老化效應為可靠度下降的主要因素，且已經達到不可忽視的程度，尤其是老化效應對電路效能衰退以及電路壽命上之影響。因此，要準確地分析老化效應所產生之電路效能衰退問題，必須同時考慮邏輯電路(logic network)跟時鐘電路(clock network)，原因是不均衡之時鐘電路老化所產生之時鐘偏移(clock skew)會大大影響電路之效能。本研究提出一個機制用以有效利用老化所產生之時鐘偏移(aging-induced clock skew)來控制電路時鐘樹之時鐘延遲時間(clock latency)，藉以降低老化所造成之電路效能衰退問題。此研究的目的在於準確地分析電路老化程度，並有效分配電路關鍵路徑(critical path)間之電路老化所產生之時鐘偏移，將電路效能衰退最小化，增加電路老化容忍度(aging tolerance)及電路壽命。

Device aging, which causes significant loss on circuit performance and lifetime, is considered as the primary factor in reliability degradation of nanoscale designs. In order for accurate analysis of circuit performance under aging, not only logic networks but also clock networks need to be considered since unbalanced aging of clock networks can greatly affect circuit performance by inducing clock skews. In this thesis, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating these time-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews for pairs of flip-flops in a circuit, such that its overall performance degradation due to aging can be minimized, that is, the lifespan can be maximized.