标题: 写入/抹除 偏压与氧化制程在快闪记忆体之可靠度研究
W/E Bias and Oxidation Process Dependence in Endurance of NAND Flash Reliability
作者: 张嘉维
白田理一郎
Chang, Chia-Wei
Riichiro, Shirota
电机工程学系
关键字: 快闪记忆体;可靠度;氧化制程;NAND Flash;endurance;reliability
公开日期: 2017
摘要: 此篇论文针对使用TEG结构之快闪记忆体在不同写入/抹除电压以及不同氧化制程之间之耐久度之研究. 穿隧氧化层之劣化被认为是目前快闪记忆体可靠度最重要的研究议题,透过特殊结构(TEG STRUCTURE)可以将浮动闸极内的电荷以及穿隧氧化层内因氧化层老化而被陷阱抓住之氧化层电荷分离,进而分析穿隧氧化层老化之物理机制. 在前一篇论文中,提出了"电子陷阱被捕之截面积(σ)",陷阱状态能阶(Etrap),在写入/抹除次数小于100次时,可解释量测到之物理现象,然而,在写入/抹除次数大于100次后尚无法找到与实验数据相符合之物理模型. 本篇论文提出"随着写入/抹除次数所产生之新能阶"之一种可能模型来解释本实验室量测到的数据,并成功在写入/抹除次数为1000次与3000次时成功解释量测现象.此模型同时也可解释湿氧化与干氧化制程,并将量测与模拟数据呈现于本篇论文中.
In order to understand the degradation mechanism in the tunnel oxide of NAND Flash memory cell, TEG structure is used, instead of conventional NAND Flash memory cell.In previous study, the endurance characteristic was analyzed. Electron trapping and de-trapping was analyzed during P/E operation. Trapping process mainly occurs after the P/E electrons tunneling through the oxide barriers. Thus, the number of trapped electrons depends on the position in the oxide. On the other hand, the trapped electrons are also de-trapped from the trap states. Thus, trapping and de-trapping process must be simultaneous calculated.By using generation rate = 10-7, the simulation result can explain three different bias (13V, 15V, 17V) under dry oxidation. The simulation also shows that using same generation rate can fit the experimental data between dry and plasma oxidation.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070450717
http://hdl.handle.net/11536/142137
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