針對以單電子電晶體為基礎的現場可程式邏輯閘陣列之架構探索及延遲最小化合成技術

Abstract

隨著製程不斷地演進，功率消耗對於電子電路與系統設計而言是一個重要的問題，而漏洩功率已逐漸成為功率消耗的主要來源。由於可重組態單電子電晶體陣列的超低功率消耗特性，已經被視為有希望延伸摩爾定律的元件之一。因為單電子電晶體在運作時只通過少量電流，因此電流無法經過很多單電子電晶體。現存的單電子電晶體合成方法是把布林電路轉成單電子電晶體陣列，陣列的高度等於輸入的個數。由於單電子電晶體的驅動力很低，單電子電晶體陣列不能任意高度。因此需要拆解單電子電晶體陣列成有限制高度的單電子電晶體陣列網路。本篇論文提出一個深度優化的合成演算法，可以拆解電路再轉換成固定大小的單電子電晶體陣列，架構會與現場可程式邏輯閘陣列類似。實驗結果顯示，不同單電子電晶體陣列大小會影響電路延遲、使用單電子電晶體陣列個數和總面積。最後我們會做架構探索並針對這些電路給出適合的單電子電晶體陣列尺寸。

As fabrication processes exploit even deeper submicron technology, power consumption has become a crucial obstacle for most electronic circuit and system designs at present. However, the leakage power is dominating the power consumption. In order to solve the leakage power problem, various innovation devices have been developed in recent years. The single-electron transistor (SET) is regarded as one of the most promising devices for continuing Moore’s Law since several works demonstrate that it can operate with only few electrons at room temperature. Currently, SET synthesis methods transform a Boolean circuit into a SET array, and the height of SET array is equal to the number of primary inputs. Since the ultra-low drivability of SET device, the height of SET array can’t be an arbitrary number. In this thesis, we propose a delay-minimized synthesis flow that decomposes a large SET array into a network of fixed-size, limited-height and limited-width, SET array blocks which is similar to lookup-table based FPGA. The experimental results show that different size of SET array block affect the delay, the number of blocks, and the area. Finally, we will do the architectural exploration, and the experimental results demonstrate the appropriate SAB sizes we suggest for minimum area and minimum ADP.