標題: 應用於高密度神經感測之低功率神經訊號放大器
Low-Power Neural Amplifier for High-Density Neural Sensing Applications
作者: 何寬倫
莊景德
黃威
Ho,Kuan-Lun
Chuang,Ching-Te
Hwang,Wei
電子研究所
關鍵字: 神經放大器;神經感測;低功率;Neural Amplifier;Neural Sensing;Low-Power
公開日期: 2017
摘要: 本論文主要目的在設計與實現一個低雜訊、低功耗四通道電生理訊號類比前端放大電路研究,可應用於各類微弱的生理訊號處理以及醫療儀器方面使用。所提出的全整合類比前端電路在處理來自輸入的生理訊號所產生的直流電壓偏移以及低頻雜訊並採用在輸入端放置大電容或是增加輸入元件面積的方法,去消除直流偏移達到最佳化的目標;為了更進一步的去縮小電路的面積而採用四個通道共用一組篇壓電路的方法使得一個通道的面積只有0.056mm2,則可在面積方面相較於其他相同應用下的電路有極大的優勢,並且加上設計上以低功耗為考量,在功耗方面也表現得十分優異。本論文設計的四通道配有folded-cascode和2-stage前端電路透過國家晶片系統設計中心使用tsmc 180nm CMOS 製成來製作晶片。模擬的結果顯示此類比前端電路可在四個通道總和面積為1000μm × 1000μm的情況下每個通道增益值達到59dB且功率消耗為1.17μW的結果;而其工作的頻寬從14.7Hz到1.94kHz。此外,CMRR與PSRR在沒有來自輸入端的直流偏壓的情況下分別可達到91.8dB以及70.1dB。
This thesis, aims to design and implement a low noise, low power-consumption 4-channel electrophysiological signal analog front-end amplifier (AFE), which can be applied to various types of weak physiological signal acquisition and medical instrumentation systems applications. Using big capacitors at the input node to block the dc offset voltage and enlarging the input device area to reduce the low frequency noise from input neural signal. To further reduce area of the circuit, adopt four channel share one biasing circuit result in only 0.056mm2 for one channel makes it have great advantages than other design. This thesis describes the design of 4-channel AFE with folded-cascode and 2-stage amplifier through the National Chip Implementation Center tsmc 180nm CMOS process. The simulation results show that the area of four channels AFE is 1000μm × 1000μm and realize 59dB gain with1.71μW for each channel. The bandwidth of the AFE is from 14.7Hz to 1.94 kHz. Furthermore, the CMRR and PSRR can reach 91.8dB and 70.1dB when there is no dc offset from the input.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070450283
http://hdl.handle.net/11536/142538
Appears in Collections:Thesis