標題: | 實作混合式執行緒架構於上行軟體實體層 Hybrid-Threading Architecture for Soft-PHY Uplink |
作者: | 辛柏輝 許騰尹 Hsin, Po-Hui 資訊科學與工程研究所 |
關鍵字: | 長期演進技術;軟體實體層;多執行緒;上行接收端;LTE;Soft PHY;Multi Thread;Uplink |
公開日期: | 2017 |
摘要: | 基於現今對於網路傳輸效率的需求,已投入眾多的人力資源於開發5G的系統規格上,而在5G逐見雛型的規格下,Soft PHY成為未來實作PHY layer的主流。此文為了解決軟體天生處理速度慢且於PHY layer綁定1 ms的運算時間限制下,提出一個基於Soft PHY的FDD多執行緒架構,在有POSIX thread(pthread)與GPU輔佐下,專注於eNB PHY layer系統架構上的多工處理運算,改善與加速當服務多使用者時提供平行化運作,使得PHY layer能夠具有更多可用的CPU timing與更高的吞吐量加速其過程。本篇論文著重於上行PHY layer之pthread運作與加速之驗證。 Based on demand for network transmission, there has invested lots of resources to develop the specification of 5G. Due to the limitation of hardware, Soft PHY becomes more and more popular to implement PHY layer. In this paper, we propose a FDD’s multi-threading architecture based on Soft PHY to improve performance for whole eNB PHY layer. Due to the limited timing(1 ms) in PHY layer, we uses Pthread to cooperate with GPU and achieve multitasking for supporting multi users. We let PHY layer have more available CPU timing and much higher throughput to speed up. This paper focuses on the operation of Pthread and the verification of speedup for PHY uplink. |
URI: | http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070456106 http://hdl.handle.net/11536/142690 |
Appears in Collections: | Thesis |