具變異感知的靜態電源電流測試與診斷技術

Abstract

靜態電源電流測試一直被用來找出潛在有缺陷的晶片，因為這些晶片的量測結果超過晶片原始設計的電氣範圍。由晶片設計預先定義的臨界值沒有考慮到製程變異的影響，由早期生產的晶片中推論出來的臨界值亦無法預測未來在晶片大量生產中的各種情況。這些以臨界值為基準的靜態電源電流測試最主要的問題即是缺少了對於製程變異的掌控。所以這篇論文主要在提出考慮了變異感知的靜態電源電流測試與診斷技術。考慮變異感知的靜態電源電流測試的概念，是要移除所有在測試過程中可能的影響，例如晶片本身的製程變異，或是測試向量使用的多寡。所以，我們提出了這個考慮變異感知的靜態電源電流測試與診斷技術，其利用一個考慮製程變異的電路電流模型，來減少晶片本身製程變異的影響。得到沒有製程變異的靜態電源電流資料後，我們便可以有效找出有缺陷的晶片，並且找出晶片內發生短路的區域。為了克服實際靜態電源電流測試法本身測試向量個 數的限制，我們亦提出了一個使用機率分布決定臨界值的分類方法。同時，我們也針對這個考慮變異感知的靜態電源電流測試與診斷技術，分析其在不同製程變異比例的能力，也分析測試向量個數及晶片個數對於此方法的影響。然而，我們發現在這個測試方法中，由測試機台上產生的量測雜訊，或是沒有考慮到的漏電流，都會影響此方法的準確度。所以我們提出設計晶片內建製程變異量測器的方式，以減少測試機台上量測雜訊的影響。因此，我們利用資料分析的方式，找出電壓源、晶片溫度、電晶體有效通道長度以及氧化層厚度為影響晶片時脈和漏電流的製程參數。我們認為基於這四個參數所設計出的晶片內建製程變異量測器，可以對製程變異有更準確的量測，以排除測試機台量測雜訊的影響，提高具變異感知的靜態電源電流測試方法的準確度；同時，也可以針對晶片的時脈有更精確的估算。由於晶片內製程量測器在晶片內擺放的位置及數量必須依據不同的電路而各別設計，所以如何設計普遍化的晶片內製程量測器以提升變異感知的靜態電源電流測試方法的準確度，以及如何將此論文提出的具變異感知的靜態電源電流測試方法實際應用到測試機台上為此研究未來的目標以方向。

Iddq testing has been used for decades to identify potential defective chips because the measurement results of those chips are out of the electrical range. Pre-defined threshold values from design specification overlooks the influence of process variations, and the threshold values defining from early-production chips may lose the predictability in future mass production. The main issue of the threshold-based Iddq testing is lack of the controllability of variations during fabrication process. Therefore, the thesis aims at developing the next-generation Iddq testing, which considers the variation in manufacturing. The concept of variation-aware Iddq testing is to remove all possible variabilities during testing, such as process variations and the number of Iddq tests. Therefore, a variation-aware Iddq testing is proposed to eliminate the process variations with a variant-aware full-chip leakage model. With the process-free Iddq, the defective chips can be filtered out and the suspect short candidates can be marked in the defective chips. To combat the limitation of test number on Iddq testing, a probability-based thresholding is developed. The variation-aware Iddq testing and diagnosis are evaluated with various conditions, such as the different amount of process variations, the influence of test pattern counts, and the impact of chip size. However, the measurement noise from tester and unknown leakage sources are big concerns in variation-aware Iddq testing. Therefore, we propose the development of an on-chip process monitor targeting few process parameters to reduce the impacts of measurement noise from the tester. In the thesis, a data analysis is applied to explore the dominant timing process parameters and dominant leakage process parameter: supply voltage, chip temperature, effective gate length, and gate oxide thickness. We believe that the design of on-chip process monitor with the four process parameters can eliminate the effect of measurement noise to improve the variation-aware Iddq testing. Meanwhile, the on-chip process monitor can also estimate the actual timing within the chip. Since the number and the location of on-chip process monitor need to be designed to consider the intra-die variation, and shall be design-dependent. The development of general-purpose on-chip process monitor becomes a future work of this research. In addition, the implementation on applying the variation-aware Iddq testing and diagnosis, and the application on other parametric testing methods are also the future works of this thesis.