標題: Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability
作者: Lin, Jer-Yi
Kumar, Malkundi Puttaveerappa Vijay
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: Junctionless (JL);inversion mode (IM);nanosheet;thin-film transistor (TFT);positive gate bias stress (PGBS)
公開日期: 1-Jan-2018
摘要: In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drivestress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits.
URI: http://dx.doi.org/10.1109/LED.2017.2779451
http://hdl.handle.net/11536/144301
ISSN: 0741-3106
DOI: 10.1109/LED.2017.2779451
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 39
起始頁: 8
結束頁: 11
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