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dc.contributor.authorLee, Shih-Weien_US
dc.contributor.authorKuo, Shu-Chiaoen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2018-08-21T05:53:21Z-
dc.date.available2018-08-21T05:53:21Z-
dc.date.issued2018-02-01en_US
dc.identifier.issn1533-4880en_US
dc.identifier.urihttp://dx.doi.org/10.1166/jnn.2018.14204en_US
dc.identifier.urihttp://hdl.handle.net/11536/144588-
dc.description.abstractA novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.en_US
dc.language.isoen_USen_US
dc.subjectThree-Dimensional (3D) Integrationen_US
dc.subjectTSVen_US
dc.subjectElectrical Measurementen_US
dc.subjectMisalignmenten_US
dc.titleA Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integrationen_US
dc.typeArticleen_US
dc.identifier.doi10.1166/jnn.2018.14204en_US
dc.identifier.journalJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGYen_US
dc.citation.volume18en_US
dc.citation.spage1066en_US
dc.citation.epage1069en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000426033000042en_US
Appears in Collections:Articles


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