標題: | 3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV) |
作者: | Shen, Wen-Wei Lin, Yu-Min Chen, Shang-Chun Chang, Hsiang-Hung Chang, Tao-Chih Lo, Wei-Chung Lin, Chien-Chung Chou, Yung-Fa Kwai, Ding-Ming Kao, Ming-Jer Chen, Kuan-Neng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Backside-via-last TSV;three-dimensional heterogeneous integration |
公開日期: | 1-一月-2018 |
摘要: | This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration. |
URI: | http://dx.doi.org/10.1109/JEDS.2018.2815344 http://hdl.handle.net/11536/144754 |
ISSN: | 2168-6734 |
DOI: | 10.1109/JEDS.2018.2815344 |
期刊: | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY |
Volume: | 6 |
起始頁: | 396 |
結束頁: | 402 |
顯示於類別: | 期刊論文 |