完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hsieh, Shang-Hsun | en_US |
dc.contributor.author | Chen, Ming-Jer | en_US |
dc.date.accessioned | 2019-04-03T06:44:26Z | - |
dc.date.available | 2019-04-03T06:44:26Z | - |
dc.date.issued | 2017-03-01 | en_US |
dc.identifier.issn | 2168-6734 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/JEDS.2017.2656883 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145449 | - |
dc.description.abstract | On the strained silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), we show how to derive a formalism dealing with the scattering of a 2-D electron by a neutral defect. The corresponding neutral defect limited inversion-layer electron mobility, mu(n), is calculated in the momentum relaxation time approximation. The calculated results lead to a new analytical model: mu(n) = cN(n)(-1) where N-n is the neutral defect density per unit area and c is the coefficient independent of the inversion-layer density, the strain, and the temperature. The validity and applicability of the model are confirmed by citing three independent experiments on strained silicon MOSFETs undergoing different implantation sources and different annealing budgets. Importantly, this paper clarifies for the first time that strain will not change neutral defect limited mobility unless changing the neutral defect density. This reasonably explains the two experimental observations during implantation and annealing: 1) the implantation-induced strain relaxation in strained sample does not occur and 2) the neutral defect density is much higher in strained sample than in unstrained sample. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Interstitial | en_US |
dc.subject | metal-oxide-semiconductor field-effect transistors (MOSFETs) | en_US |
dc.subject | mobility | en_US |
dc.subject | neutral defect | en_US |
dc.subject | scattering | en_US |
dc.subject | strain | en_US |
dc.title | A Model for Neutral Defect Limited Electron Mobility in Strained-Silicon Inversion Layers | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/JEDS.2017.2656883 | en_US |
dc.identifier.journal | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | en_US |
dc.citation.volume | 5 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 101 | en_US |
dc.citation.epage | 106 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000400467500001 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |